One important technique for fabricating a semiconductor device involves forming a connection between an upper level wiring layer and either a conductive region of an impurity-diffused layer in a semiconductor substrate or a lower level wiring layer. Such a connection is preferably formed through a contact hole formed in an interlayer insulating film.
Recently as the density of integrated circuits has increased, the design rule, i.e., the minimum feature size, has decreased. As a result, the distance between gate stacks in a semiconductor device is being shortened to coordinate this reduced design rule. Accordingly, a contact hole opened in the interlayer insulating layer between the gate stacks has a high aspect ratio and an over-etch is implemented during a step of etching the interlayer insulating layer. However, such an over-etch may also etch a silicon nitride gate spacer that operates to protect the gate stacks.
FIGS. 1A to 1D are cross-sectional views at selected stages of a conventional fabrication process for forming a contact hole between gate stacks. FIG. 1A schematically shows a semiconductor substrate 10 having a cell array region and a core region, each area having a plurality of gate stacks 18. Each gate stack 18 includes a gate oxide layer 11, a gate electrode 15, and a silicon nitride capping layer 16. The gate electrode 15 is generally made of a multilayer structure of a polysilicon layer 12 and a tungsten silicide layer 14. A first silicon nitride layer 20 is generally deposited over the entire surface of the semiconductor substrate 10 and the plurality of gate stacks 18 by a conventional method such as chemical vapor deposition (CVD).
The first silicon nitride layer 20 is then etched back to form spacers 21 on both sidewalls of the gate stacks 18 as shown in FIG. 1B. A second silicon nitride layer 22 is then deposited over the resulting structure, including the substrate 10 and the gate stacks 18, to serve as an etching stopper. An interlayer insulating layer 24 is then deposited over the gate stacks 18 and in the spaces between the gate stacks 18.
Referring to FIG. 1C, selected portions of the interlayer insulating layer 24 are etched to form a plurality of contact holes 26 between the gate stacks 18 using the second silicon nitride layer 22 as an etching stopper.
After forming the contact holes 26, the second silicon nitride layer 22 between the gate stacks is removed as shown in FIG. 1D.
The above-mentioned method uses silicon nitride for the capping layer 16, the gate spacer 21, and the etching stopper 22. As a result, the gate spacer 21 and the capping layer 16 are also etched during the step of etching the second silicon nitride layer 22, as shown in inside the dotted circle of FIG. 1D. Accordingly, the gate electrode 15 may electrically contact the subsequently-formed conductive bit line and storage node pads (or landing pads).